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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. AM42BDS6408H data sheet publication number 30491 revision a amendment +3 issue date october 23, 2003
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advance information this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. amd re- serves the right to change or discontinue work on this proposed product without notice. publication# 30491 rev: a amendment: +3 issue date: october 23, 2003 refer to amd?s website (www.amd.com) for the latest information. AM42BDS6408H am29bds640h 64 megabit (4 m x 16-bit) stacked multichip package (mcp) flash memory and sram cmos 1.8 volt-only simultaneous read/write, burst mode flash memory, and 8 mbit (512 k x 16-bit) sram flash distinctive characteristics architectural advantages single 1.8 volt read, program and erase (1.65 to 1.95 volt) manufactured on 0.13 m process technology versatileio? (v io ) feature ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.8v compatible i/o signals ? contact factory for availability of 1.5v compatible i/o signals simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? four bank architecture: 8mb/24mb/24mb/8mb programable burst interface ? 2 modes of burst read operation ? linear burst: 8, 16, and 32 words with wrap-around ? continuous sequential burst secsi tm (secured silicon) sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words sector architecture ? sixteen 4 kword sectors and one hundred twenty-six 32 kword sectors ? banks a and d each contain eight 4 kword sectors and fifteen 32 kword sectors; banks b and c each contain forty-eight 32 kword sectors ? sixteen 4 kword boot sectors: eight at the top of the address range and eight at the bottom of the address range minimum 1 million erase cycle guarantee per sector 20-year data retention at 125c ? reliable operation for the life of the system 89-ball fbga package performance charcteristics read access times at 66/54 mhz (c l =30 pf) ? burst access times of 11/13.5 ns at industrial temperature range ? synchronous latency of 56/69 ns ? asynchronous random access times of 45/50/55 ns power dissipation (typical values, c l = 30 pf) ? burst mode read: 10 ma ? simultaneous operation: 25 ma ? program/erase: 15 ma ? standby mode: 0.2 a hardware features handshaking feature ? provides host system with minimum possible latency by monitoring rdy ? reduced wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses hardware reset input (reset#) ? hardware method to reset the device for reading array data wp# input ? write protect (wp#) function allows protection of the four highest and four lowest 4 kword boot sectors, regardless of sector protect status persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password acc input: acceleration function reduces programming time; all sectors locked when acc = v il
2 AM42BDS6408H october 23, 2003 advance information cmos compatible inputs, cmos compatible outputs low v cc write inhibit software features supports common flash memory interface (cfi) software command set compatible with jedec 42.4 standards ? backwards compatible with am29f and am29lv families data# polling and toggle bits ? provides a software method of detecting program and erase operation completion erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences burst suspend/resume ? suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state sram features power dissipation ? operating: 10 ma typical ? standby: 2 a ce1s# and ce2 chip select power down features using ce1s# and ce2s data retention supply voltage: 1.0 to 2.2 volt byte data control: lb# (dq7-dq0), ub#s (dq15-dq8)
october 23, 2003 AM42BDS6408H 3 advance information general description the am29bds640h is a 64 mbit, 1.8 volt-only, simultaneous read/write, burst mode flash memory device, organized as 4,194,304 words of 16 bits each. this device uses a single v cc of 1.65 to 1.95 v to read, program, and erase the mem- ory array. a 12.0-volt v hh on acc may be used for faster program performance if desired. at 66 mhz, the device provides a burst access of 11 ns at 30 pf with a latency of 56 ns at 30 pf.at 54 mhz, the device provides a burst access of 13.5 ns at 30 pf with a latency of 69ns at 30 pf. the device operates within the industrial tem- perature range of -40c to +85c. the device is offered in the 64-ball fbga package. the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into four banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from wait- ing for the completion of program or erase operations. the device is divided as shown in the following table: the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates at its data out- puts and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. the device uses chip enable (ce#), write enable (we#), address valid (avd#) and output enable (oe#) to control asynchronous read and write operations. for burst opera- tions, the device additionally requires ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. the burst read mode feature gives system designers flexibil- ity in the interface to the device. the user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. the clock polarity feature provides system designers a choice of active clock edges, eit her rising or falling. the ac- tive clock edge initiates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read boot-up firm- ware from the flash memory device. the host system can detect whether a program or erase op- eration is complete by using the device status bit dq7 (data# polling) and dq6/dq2 (t oggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. the device also offers two types of data protection at the sector level. when at v il , wp# locks the four highest and four lowest boot sectors. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power con- sumption is greatly reduced in both modes. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunnelling. the data is programmed using hot electron injection. bank quantity size a 84 kwords 15 32 kwords b 48 32 kwords c 48 32 kwords d 15 32 kwords 84 kwords
4 AM42BDS6408H october 23, 2003 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 6 flash memory block diagram. . . . . . . . . . . . . . . . 7 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 9 special handling instructions for fbga package .......................... 9 ordering information . . . . . . . . . . . . . . . . . . . . . . 11 device bus operations . . . . . . . . . . . . . . . . . . . . . 12 table 1. device bus operations ..........................................................12 versatileio? (v io ) control .......................................................... 12 requirements for asynchronous read operation (non-burst) .................................................................. 12 requirements for synchronous (burst) read operation ............. 12 8-, 16-, and 32-word linear burst with wrap around .................. 13 table 2. burst address groups .............................................................13 burst suspend/resume ............................................................... 13 configuration register ................................................................. 14 reduced wait-state handshaking option .................................... 14 simultaneous read/write operations with zero latency ............ 14 writing commands/command sequences .................................. 14 accelerated program operation ................................................... 15 table 3. AM42BDS6408H boot sector/sector block addresses for protec- tion/unprotection ...................................................................................16 sector/sector block protection and unprotection ........................ 16 sector protection .......................................................................... 16 selecting a sector protection mode ............................................. 16 persistent sector protection ......................................................... 17 persistent protection bit (ppb) .................................................... 17 persistent protection bit lock (ppb lock) ................................... 17 dynamic protection bit (dyb) ...................................................... 17 table 4. sector protection schemes .....................................................18 persistent sector protection mode locking bit ............................ 18 password protection mode .......................................................... 18 password and password mode locking bit ................................. 19 64-bit password ........................................................................... 19 persistent protection bit lock ...................................................... 19 high voltage sector protection .................................................... 19 standby mode .............................................................................. 19 automatic sleep mode ................................................................. 20 reset#: hardware reset input .................................................. 20 output disable mode ................................................................... 20 figure 1. temporary sector unprotect operation................................. 20 figure 2. in-system sector protection/ sector unprotection algorithms ............................................................ 21 secsi? (secured silicon) sector flash memory region .................................................................. 22 factory-locked area (64 words) .................................................. 22 table 5. secsi tm sector addresses .....................................................22 customer-lockable area (64 words) ........................................... 22 secsi sector protection bits ........................................................ 22 hardware data protection ............................................................ 22 write protect (wp#) ..................................................................... 23 low v cc write inhibit ................................................................... 23 write pulse ?glitch? protection ..................................................... 23 logical inhibit ............................................................................... 23 power-up write inhibit ................................................................. 23 table 6. cfi query identification string ................................................23 table 7. system interface string........................................................... 24 table 8. device geometry definition .................................................... 24 table 9. primary vendor-specific extended query ..............................25 table 10. sector address table ........................................................... 26 command definitions . . . . . . . . . . . . . . . . . . . . . 30 reading array data ...................................................................... 30 set configuration register command sequence ........................ 30 figure 3. synchronous/asynchronous state diagram .......................... 30 read mode setting ...................................................................... 30 programmable wait state configuration ...................................... 30 table 11. programmable wait state settings ....................................... 31 reduced wait-state handshaking option .................................... 31 table 12. wait states for reduced wait-state handshaking ............... 32 standard handshaking option ..................................................... 32 table 13. wait states for standard handshaking ................................. 32 read mode configuration ............................................................ 32 table 14. read mode settings ............................................................. 33 burst active clock edge configuration ........................................ 33 rdy configuration ....................................................................... 33 table 15. configuration register .......................................................... 33 reset command .......................................................................... 33 autoselect command sequence .................................................. 34 enter secsi? sector/exit secsi sector command sequence ................................................................... 34 program command sequence ..................................................... 34 unlock bypass command sequence ........................................... 35 figure 4. program operation ................................................................ 35 chip erase command sequence ................................................. 35 sector erase command sequence .............................................. 36 erase suspend/erase resume commands ................................ 36 figure 5. erase operation .................................................................... 37 password program command ..................................................... 37 password verify command .......................................................... 37 password protection mode locking bit program command ....... 37 persistent sector protection mode locking bit program command 38 secsi sector protection bit program command .......................... 38 ppb lock bit set command ........................................................ 38 dyb write command ................................................................... 38 password unlock command ........................................................ 38 ppb program command .............................................................. 38 all ppb erase command ............................................................. 39 dyb write command ................................................................... 39 ppb status command ................................................................. 39 ppb lock bit status command ................................................... 39 dyb status command ................................................................. 39 command definitions ................................................................... 40 table 16. command definitions .......................................................... 40 write operation status . . . . . . . . . . . . . . . . . . . . 43 dq7: data# polling ...................................................................... 43 figure 6. data# polling algorithm ......................................................... 43 dq6: toggle bit i .......................................................................... 44 figure 7. toggle bit algorithm .............................................................. 45 ..................................................................................................... 45 dq2: toggle bit ii ......................................................................... 45 table 17. dq6 and dq2 indications ..................................................... 46 reading toggle bits dq6/dq2 .................................................... 46 dq5: exceeded timing limits ...................................................... 46 dq3: sector erase timer ............................................................. 46 table 18. write operation status ......................................................... 47 absolute maximum ratings . . . . . . . . . . . . . . . . 48 figure 8. maximum negative overshoot waveform ............................. 48 figure 9. maximum positive overshoot waveform .............................. 48
october 23, 2003 AM42BDS6408H 5 advance information operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 48 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . 49 sram dc and operating characteristics . . . . . . 50 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. test setup............................................................................ 51 table 19. test specifications ................................................................51 key to switching waveforms . . . . . . . . . . . . . . . 51 switching waveforms . . . . . . . . . . . . . . . . . . . . . 51 figure 11. input waveforms and measurement levels ........................ 51 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 v cc power-up .............................................................................. 52 figure 12. v cc power-up diagram ....................................................... 52 synchronous/burst read (v io = 1.8 v) ........................................ 53 figure 13. clk synchronous burst mode read (rising active clk)..... 54 figure 14. clk synchronous burst mode read (falling active clock) 54 figure 15. synchronous burst mode read ........................................... 55 figure 16. 8-word linear burst with wrap around ................................ 55 figure 17. linear burst with rdy set one cycle before data ............. 56 figure 18. reduced wait-state handshake burst suspend/resume at an even address......................................................................................... 57 figure 19. reduced wait-state handshake burst suspend/resume at an odd address .......................................................................................... 57 figure 20. reduced wait-state handshake burst suspend/resume at ad- dress 3eh (or offset from 3eh) .............................................................. 58 figure 21. reduced wait-state handshake burst suspend/resume at ad- dress 3fh (or offset from 3fh by a multiple of 64) ................................ 58 figure 22. standard handshake burst suspend prior to initial access 59 figure 23. standard handshake burst suspend at or after inital access .. 59 figure 24. standard handshake burst suspend at address 3fh (starting address 3dh or earlier) ......................................................................... 60 figure 25. standard handshake burst suspend at address 3eh/3fh (with- out a valid initial access)....................................................................... 60 figure 26. standard handshake burst suspend at address 3eh/3fh (with 1 access clk) ...................................................................................... 61 figure 27. read cycle for continuous suspend................................... 61 asynchronous mode read (v io = 1.8 v) ...................................... 62 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 28. asynchronous mode read with latched addresses ........... 63 figure 29. asynchronous mode read................................................... 63 figure 30. reset timings...................................................................... 64 erase/program operations (v io = 1.8 v) ..................................... 65 figure 31. asynchronous program operation timings: avd# latched ad- dresses ................................................................................................. 66 figure 32. asynchronous program operation timings: we# latched ad- dresses ................................................................................................. 67 figure 33. synchronous program operation timings: we# latched ad- dresses ................................................................................................. 68 figure 34. synchronous program operation timings: clk latched ad- dresses ................................................................................................. 69 figure 35. chip/sector erase command sequence............................. 70 figure 36. accelerated unlock bypass programming timing .............. 71 figure 37. data# polling timings (during embedded algorithm) ......... 72 figure 38. toggle bit timings (during embedded algorithm) .............. 72 figure 39. synchronous data polling timings/toggle bit timings....... 73 figure 40. dq2 vs. dq6 ....................................................................... 73 temporary sector unprotect ........................................................ 74 figure 41. temporary sector unprotect timing diagram ..................... 74 figure 42. sector/sector block protect and unprotect timing diagram .................................................................... 75 figure 43. latency with boundary crossing ......................................... 76 figure 44. latency with boundary crossing into program/erase bank...................................................................... 77 figure 45. example of wait states insertion ........................................ 78 figure 46. back-to-back read/write cycle timings............................. 79 sram ac characteristics . . . . . . . . . . . . . . . . . . 80 read cycle ................................................................................... 80 figure 47. sram read cycle?address controlled ............................ 80 figure 48. sram read cycle............................................................... 81 write cycle ................................................................................... 82 figure 49. sram write cycle?we# control....................................... 82 figure 50. sram write cycle?ce1#s control.................................... 83 figure 51. sram write cycle?ub#s and lb#s control...................... 84 erase and programming performance . . . . . . . 85 bga ball capacitance . . . . . . . . . . . . . . . . . . . . . 85 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 86 tlb 089?89-ball fine-pitch ball grid array (fbga) 10 x 8 mm package ............................................................................. 86 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 87
6 AM42BDS6408H october 23, 2003 advance information product selector guide note: speed options ending in ?8? and ?6? indicate the ?reduced wait-state handshaking? option, which speeds initial synchronous accesses for even addresses. speed options ending in ?9? and ?7? indicate the ?standard handshaking? option. see the ac characteristics section of this datasheet for full specifications. part number AM42BDS6408H burst frequency 66 mhz 54 mhz speed option v cc , v io = 1.65 ? 1.95 v e8, e9 e3, e4 d8, d9 d3, d4 flash max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking; even address 56 56 69 69 max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking; odd address; or standard handshaking 71 71 87.5 87.5 max burst access time, ns (t bacc ) 11 13.5 max asynchronous access time, ns (t acc ) 50 50 55 55 max ce# access time, ns (t ce ) max oe# access time, ns (t oe ) 11 13.5 sram max access time, ns (t acc ) 705570 55 max ce# access time, ns (t ce ) 705570 55 max oe# access, ns (t oe ) 352535 25
october 23, 2003 AM42BDS6408H 7 advance information flash memory block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v ssio v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a21?a0 rdy buffer rdy burst state control burst address counter avd# clk
8 AM42BDS6408H october 23, 2003 advance information block diagram of simultaneous operation circuit v ss v cc v io bank b address reset# acc we# ce# avd# rdy dq15?dq0 wp# state control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# status control a21?a0 a21?a0 a21?a0 a21?a0 a21?a0 bank c address bank d address bank a address
october 23, 2003 AM42BDS6408H 9 advance information connection diagram special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150c for prolonged periods of time. g2 g3 g4 g5 g6 g7 g8 f1 f2 f3 f4 f5 f6 f7 f8 e1 e2 e3 e4 e5 e6 e7 e8 d2 d3 d4 d5 d6 d7 d8 c2 c3 c4 c5 c6 c7 c8 b1 b2 b3 b4 b5 b6 b7 b8 a8 a11 we# acc lb# a7 wp# nc a1 a2 a3 a4 a5 a6 a7 a8 nc nc nc nc clk v ss adv# nc a19 a12 ce2s reset# ub# a6 a3 a9 a13 a20 rdy a18 a5 a2 a10 a14 nc nc a17 a4 a1 nc dq6 nc nc nc dq1 v ss a0 nc dq13 dq15 dq4 dq3 dq9 oe# ce#f h2 h3 h4 h5 h6 h7 h8 dq12 dq7 v cc s v cc f dq10 dq0 ce1#s g9 f9 f10 e9 e10 d9 c9 b9 nc a9 a10 nc nc a15 a21 nc nc a16 nc nc h9 v ss j2 j3 j4 j5 j6 j7 j8 dq5 dq14 nc dq11 dq2 dq8 nc k1 k2 k3 k4 k5 k6 k7 k8 nc nc nc v io f v ss nc nc nc j9 nc k9 k10 nc nc flash only sram only 89-ball fine-pitch ball grid array (top view, balls facing down)
10 AM42BDS6408H october 23, 2003 advance information pin description a18?a0 = 19 address inputs (common) a21?a19 = 3 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce1#s = chip enable 1 (sram) ce2s = chip enable 2 (sram) oe# = output enable (common) we# = write enable (common) ub#s = upper byte control (sram) lb#s = lower byte control (sram) reset# = hardware reset pin, active low v cc f = flash 1.8 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io f = input & output buffer power supply must be tied to v cc . v cc s = sram power supply v ssio f = output buffer ground v ss = device ground (common) nc = pin not connected internally rdy = ready output; indicates the status of the burst read. low = data not valid at expected time. high = data valid. clk = clk is not required in asynchronous mode. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. avd# = address valid input. indicates to de- vice that the valid address is present on the address inputs (a21?a0). low = for asynchronous mode, indi- cates valid address; for burst mode, causes starting address to be latched. high = device ignores address in- puts wp# = hardware write protect input. at v il , disables program and erase func- tions in the two outermost sectors. should be at v ih for all other condi- tions. acc = at v id , accelerates programming; automatically places device in un- lock bypass mode. at v il , locks all sectors. should be at v ih for all other conditions. logic symbol 19 16 dq15?dq0 a18?a0 ce#f oe# we# reset# ub#s rdy wp# a21?a19 lb#s acc ce1#s ce2s avd# clk
october 23, 2003 AM42BDS6408H 11 advance information ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to con- firm availability of specific valid combinations and to check on newly released combinations. note: for the am29bds640h, the last digit of the speed grade specifies the v io range of the device. speed options ending in ?8? and ?9? (e.g., d8, d9) indicate a 1.8 volt v io range. am42bds6408 h d 8 i t tape and reel t =7 inches s =13 inches temperature range i = industrial (?40 c to +85 c) handshaking options + sram speed 8 = reduced wait-state handshaking enabled + 70 ns sram 9 = standard handshaking + 70 ns sram 3 = reduced wait-state handshaking enabled + 55 ns sram 4 = standard handshaking + 55 ns sram speed e=66 mhz d= 54 mhz process technology h = 0.13 um device number/description AM42BDS6408H 64 megabit (4 m x 16-bit) cmos flash memory, simultaneous read/write, burst mode flash memory, 1.8 volt-only read, program, and erase 8 mb (512 k x 16-bit) sram wp# at v il level protects top and bottom sectors valid combinations flash burst frequency (mhz) sram speed (ns) order number package marking AM42BDS6408He8 i m420000070 66 70 AM42BDS6408He9 m420000071 AM42BDS6408Hd8 m420000072 54 AM42BDS6408Hd9 m420000073 AM42BDS6408He3 m420000074 66 55 AM42BDS6408He4 m420000075 AM42BDS6408Hd3 m420000076 54 AM42BDS6408Hd4 m420000077
12 AM42BDS6408H october 23, 2003 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the func- tion of the device. ta b l e 1 lists the device bus opera- tions, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic 0, h = logic 1, x = don?t care, s = stable logic 0 or 1 but no transitions. note: default active edge of clk is the rising edge. versatileio? (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must first assert a valid address on a21?a0, while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15?dq0. since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. this ensures that no spurious alter- ation of the memory content occurs during the power transition. requirements for synchronous (burst) read operation the device is capable of continuous sequential burst operation and linear burst operation of a preset length. operation ce# oe# we# a21?0 dq15?0 reset# clk (see note) avd# asynchronous read - addresses latched l l h addr in i/o h x asynchronous read - addresses steady state l l h addr in i/o h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x high z high z h x x hardware reset x x x high z high z l x x burst read operations load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus llhhigh z burst data out hh terminate current burst read cycle h x h high z high z h x terminate current burst read cycle via reset# x x h high z high z l x x terminate current burst read cycle and start new burst read cycle l x h high z i/o h
october 23, 2003 AM42BDS6408H 13 advance information when the device first powers up, it is enabled for asyn- chronous read operation. prior to entering burst mode, the system should deter- mine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the rdy signal will transi- tion with valid data. the system would then write the configuration register command sequence. see ?set configuration register command sequence? section on page 30 and ?command definitions? section on page 30 for further details. once the system has written the ?set configuration register? command sequence, the device is enabled for synchronous reads only. the initial word is output t iacc after the active edge of the first clk cycle. subsequent words are output t bacc after the active edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003fh. during the time the device is out- putting data at this fixed internal address boundary (address 00003fh, 00007fh, 0000bfh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000c0h, etc.). the rdy output indicates this condition to the system by pulsing low. for standard handshaking devices, there is no two cycle latency between 3fh and 40h (or offset from these values by a multiple of 64) if the latched address was 3eh or 3fh (or offset from these values by a multiple of 64). see figure 43, ?latency with boundary crossing,? on page 76 . for reduced wait-state handshaking devices, if the address latched is 3eh or 3fh (or offset from these values by a multiple of 64) two additional cycle latency occurs prior to the initial access and the two cycle latency between 3fh and 40h (or offset from these values by a multiple of 64) will not occur. the device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. see table 1, ?device bus operations,? on page 12 . if the host system crosses the bank boundary while reading in burst mode, and the device is not program- ming or erasing, a two-cycle latency will occur as described above in the subsequent bank. if the host system crosses the bank boundary while the device is programming or erasing, the device will provide read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse. if the clock frequency is less than 6 mhz during a burst mode operation, additional latencies will occur. rdy indicates the length of the latency by pulsing low. 8-, 16-, and 32-word linear burst with wrap around the remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 2 .) table 2. burst address groups as an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be 39-3a-3b-3c-3d-3e-3f-38h-etc. the burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the initial access). the rdy pin indicates when data is valid on the bus. the devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). burst suspend/resume the burst suspend/resume feature allows the system to temporarily suspend a synchronous burst operation during the initial access (before data is available) or after the device is outputting data. when the burst operation is suspended, any previously latched internal data and the current state are retained. burst suspend requires ce# to be asserted, we# de-asserted, and the initial address latched by avd# or the clk edge. burst suspend occurs when oe# is de-asserted. see figure 18, ?reduced wait-state handshake burst suspend/resume at an even address,? on page 57, figure 19, ?reduced wait-state handshake burst suspend/resume at an odd address,? on page 57, figure 20, ?reduced wait-state mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
14 AM42BDS6408H october 23, 2003 advance information handshake burst suspend/resume at address 3eh (or offset from 3eh),? on page 58, figure 21, ?reduced wait-state handshake burst suspend/resume at address 3fh (or offset from 3fh by a multiple of 64),? on page 58, figure 22, ?standard handshake burst suspend prior to initial access,? on page 59, figure 23, ?standard handshake burst suspend at or after inital access,? on page 59, figure 24, ?standard handshake burst suspend at address 3fh (starting address 3dh or earlier),? on page 60, figure 25, ?standard hand- shake burst suspend at address 3eh/3fh (without a valid initial access),? on page 60, and figure 26, ?stan- dard handshake burst suspend at address 3eh/3fh (with 1 access clk),? on page 61. burst plus burst suspend should not last longer than t rcc without re-latching an address or crossing an address boundary. to resume the burst access, oe# must be re-asserted. the next active clk edge will resume the burst sequence where it had been sus- pended. see , figure 27, ?read cycle for continuous suspend,? on page 61. the rdy pin is only controlled by ce#. rdy will remain active and is not placed into a high-impedance state when oe# is de-asserted. configuration register the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. reduced wait-state handshaking option the device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the rdy signal from the device to deter- mine when the initial word of burst data is ready to be read. the host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. the presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. see ?autoselect command sequence? for details. for optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. see ?set configuration register command sequence? section on page 30 section for more information. the device will automatically delay rdy and data by one additional clock cycle when the starting address is odd. the autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. see the ?autoselect command sequence? section for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). figure 46, ?back-to-back read/write cycle timings,? on page 79 shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has the capability of performing an asyn- chronous or synchronous write operation. while the device is configured in asynchronous read it is able to perform asynchronous write operations only. clk is ignored in the asynchronous programming mode. when in the synchronous read mode configuration, the device is able to perform both asynchronous and syn- chronous write operations. clk and we# address latch is supported in the synchronous programming mode. during a synchronous write operation, to write a command or command sequence (which includes pro- gramming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asynchro- nous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. the asynchronous and synchronous programing operation is independent of the set device read mode bit in the configuration register (see table 15, ?configuration register,? on page 33 ). the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 10, ?sector address table,? on page 26 indicates the address space that each sector occupies. the device address space is divided into four banks: banks b and c contain only 32 kword sectors, while banks a and d contain both 4 kword boot sectors in addition to 32 kword sectors. a
october 23, 2003 AM42BDS6408H 15 advance information ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in the ?dc characteristics? section on page 49 represents the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write oper- ations. accelerated program operation the device offers accelerated program operations through the acc function. acc is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this input, the device auto- matically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the acc input returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v hh . note that the acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions.
16 AM42BDS6408H october 23, 2003 advance information table 3. AM42BDS6408H boot sector/sector block addresses for protection/unprotection sector/sector block protection and un- protection the hardware sector protection feature disables both programming and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection can be imple- mented via two methods. (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ta bl e 3 , ?AM42BDS6408H boot sector/sector block addresses for protection/unprotection,? on page 16 sector protection the AM42BDS6408H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in the outermost sectors. the wp# hardware protection feature is always avail- able, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent sector protection mode. the customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to con- tinue using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this will permanently set the part to op- sector a21?a12 sector/ sector block size sa0 0000000000 4 kwords sa1 0000000001 4 kwords sa2 0000000010 4 kwords sa3 0000000011 4 kwords sa4 0000000100 4 kwords sa5 0000000101 4 kwords sa6 0000000110 4 kwords sa7 0000000111 4 kwords sa8 0000001xxx 32 kwords sa9 0000010xxx 32 kwords sa10 0000011xxx 32 kwords sa11?sa14 00001xxxxx 128 (4x32) kwords sa15?sa18 00010xxxxx 128 (4x32) kwords sa19?sa22 00011xxxxx 128 (4x32) kwords sa23-sa26 00100xxxxx 128 (4x32) kwords sa27-sa30 00101xxxxx 128 (4x32) kwords sa31-sa34 00110xxxxx 128 (4x32) kwords sa35-sa38 00111xxxxx 128 (4x32) kwords sa39-sa42 01000xxxxx 128 (4x32) kwords sa43-sa46 01001xxxxx 128 (4x32) kwords sa47-sa50 01010xxxxx 128 (4x32) kwords sa51?sa54 01011xxxxx 128 (4x32) kwords sa55?sa58 01100xxxxx 128 (4x32) kwords sa59?sa62 01101xxxxx 128 (4x32) kwords sa63?sa66 01110xxxxx 128 (4x32) kwords sa67?sa70 01111xxxxx 128 (4x32) kwords sa71?sa74 10000xxxxx 128 (4x32) kwords sa75?sa78 10001xxxxx 128 (4x32) kwords sa79?sa82 10010xxxxx 128 (4x32) kwords sa83?sa86 10011xxxxx 128 (4x32) kwords sa87?sa90 10100xxxxx 128 (4x32) kwords sa91?sa94 10101xxxxx 128 (4x32) kwords sa95?sa98 10110xxxxx 128 (4x32) kwords sa99?sa102 10111xxxxx 128 (4x32) kwords sa103?sa106 11000xxxxx 128 (4x32) kwords sa107?sa110 11001xxxxx 128 (4x32) kwords sa111?sa114 11010xxxxx 128 (4x32) kwords sa115?sa118 11011xxxxx 128 (4x32) kwords sa119?sa122 11100xxxxx 128 (4x32) kwords sa123?sa126 11101xxxxx 128 (4x32) kwords sa127?sa130 11110xxxxx 128 (4x32) kwords sa131 1111100xxx 32 kwords sa132 1111101xxx 32 kwords sa133 1111110xxx 32 kwords sa134 1111111000 4 kwords sa135 1111111001 4 kwords sa136 1111111010 4 kwords sa137 1111111011 4 kwords sa138 1111111100 4 kwords sa139 1111111101 4 kwords sa140 1111111110 4 kwords sa141 1111111111 4 kwords sector a21?a12 sector/ sector block size
october 23, 2003 AM42BDS6408H 17 advance information erate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this will permanently set the part to operate only using pass- word sector protection. it is important to remember that setting either the per- sistent sector protection mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at the factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see ?autoselect command se- quence? section on page 33 for details. persistent sector protection the persistent sector protection method replaces the old 12 v controlled protection method while at the same time enhancing flexibility by providing three dif- ferent sector protection states: persistently locked ?a sector is protected and cannot be changed. dynamically locked ?the sector is protected and can be changed by a simple command unlocked ?the sector is unprotected and can be changed by a simple command in order to achieve these states, three types of ?bits? are going to be used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is as- signed to a maximum four sectors ( ?AM42BDS6408H boot sector/sector block addresses for protec- tion/unprotection? section on page 16 ). all 4 kbyte boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb program command . note: if a ppb requires erasure, all of the sector ppbs must first be preprogrammed prior to ppb erasing. all ppbs erase in parallel, unlike programming where in- dividual ppbs are programmable. it is the responsibil- ity of the user to perform the preprogramming operation. otherwise, an already erased sector ppbs has the potential of being over-erased. there is no hardware mechanism to prevent sector ppbs over-erasure. persistent protection bit lock (ppb lock) a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per de- vice. the ppb lock is cleared after power-up or hard- ware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared. the dybs and ppb lock are defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the pbb lock bit adds an addi tional level of protec- tion. once all ppbs are programmed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the
18 AM42BDS6408H october 23, 2003 advance information ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp# write protect pin adds a final level of hard- ware protection to the four highest and four lowest 4 kbyte sectors (sa0 - sa3, sa138 - sa141 for a dual boot). when this pin is low it is not possible to change the contents of these four sectors. these sectors gen- erally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could over- ride the choices made while setting up sector protec- tion during system initialization. it is possible to have sectors that have been persis- tently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unpro- tected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and un- protected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the de- vice operates normally again. note: to achieve the best protection, it?s recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . table 4. sector protection schemes ta b l e 4 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynami- cally locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modi- fied the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sec- tor. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a persistent sec- tor protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit pre- vents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode method allows an even higher level of security than the persistent sector protection mode. there are two main differ- ences between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes out of a reset cycle, the ppb lock bit is set to the locked state , rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writ- ing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region of the flash memory. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the pass- word unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-pro- dyb ppb ppb lock sector state 000 unprotected?ppb and dyb are changeable 001 unprotected?ppb not changeable, dyb is changeable 010 protected?ppb and dyb are changeable 100 110 011 protected?ppb not changeable, dyb is changeable 101 111
october 23, 2003 AM42BDS6408H 19 advance information grammed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the pass- word. amd recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each pass- word should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to re- verse this function. 2. it also disables all further commands to the pass- word region. all program, and read operations are ignored. both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection lock- ing bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the pass- word program and verify commands (see ?password program command? section on page 37 and ?pass- word verify command? section on page 37 ). the password function works in conjunction with the pass- word mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode lock- ing bit after power-up reset. if the password mode lock bit is also set, after a hardware reset (reset# asserted) or a power-up reset the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. suc- cessful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1?. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set com- mand. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persis- tent protection mode. high voltage sector protection sector protection and unprotection may also be imple- mented using programming equipment. the procedure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 2, ?in-system sector pro- tection/ sector unprotection algorithms,? on page 21 for details on this procedure. note that for sector unpro- tect, all unprotected sectors must be first protected prior to the first sector write cycle. once the password mode locking bit or persistent protection locking bit are set, the high voltage sector protect/unprotect capa- bility is disabled. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the opera- tion is completed. i cc3 in the ?dc characteristics? section on page 49 represents the standby current specification.
20 AM42BDS6408H october 23, 2003 advance information automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 60 ns. the auto- matic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. while in synchronous mode, the device automatically enables this mode when either the first active clk level is greater than t acc or the clk runs slower than 5 mhz. note that a new burst opera- tion is required to provide new data. i cc6 in the ?dc characteristics? section on page 49 represents the automatic sleep mode current specifica- tion. reset#: hardware reset input the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase oper- ation, the device requires a time of t ready (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ?ac characteristics? section on page 64 for reset# parameters and to figure 30, ?reset tim- ings,? on page 64 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high imped- ance state. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp# = v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again.
october 23, 2003 AM42BDS6408H 21 advance information figure 2. in-system sector protection/ sector unprotection algorithms sector protect: write 60h to sector address with a7 ? a0 = 00000010 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7 ? a0 = 00000010 read from sector address with a7 ? a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7 ? a0 = 01000010 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a7 ? a0 = 00000010 read from sector address with a7 ? a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
22 AM42BDS6408H october 23, 2003 advance information secsi? (secured silicon) sector flash memory region the secsi (secured silicon) se ctor feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secsi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secsi sector is located at addresses 000000h-00007fh in both persistent pro- tection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the fac- tory-locked and customer-locked status of the part. the system accesses the secsi sector through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to send- ing commands to the normal address space. factory-locked area (64 words) the factory-locked area of the secsi sector (000000h-00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secsi sector factory-locked indicator bit (dq7) is permanently set to a ?1?. amd offers the expressflash service to program the factory-locked area with a random esn, a customer-defined code, or any combination of the two. because only amd can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact an amd repre- sentative for details on using amd?s expressflash ser- vice. table 5. secsi tm sector addresses customer-lockable area (64 words) the customer-lockable area of the secsi sector (000040h-00007fh) is shipped unprotected, which al- lows the customer to program and optionally lock the area as appropriate for the application. the secsi sector customer-locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secsi protection bit program command. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock by- pass functions are not available when programming the secsi sector. the customer-lockable secsi sector area can be pro- tected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector re- gion without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. write the three-cycle enter secsi sector secure region command sequence, and then use the alter- nate method of sector protection described in the high voltage sector protection section. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region com- mand sequence to return to reading and writing the remainder of the array. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. secsi sector protection bits the secsi sector protection bits prevent program- ming of the secsi sector memory area. once set, the secsi sector memory area contents are non-modifi- able. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta bl e 1 6 , ? c o m - mand definitions,? on page 40 for command defini- tions). the device offers two types of data protection at the sector level: the ppb and dyb associated command se- quences disables or re-enables both program and erase operations in any sector or sector group. when wp# is at v il , the four outermost sectors are locked. when acc is at v il , all sectors are locked. the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transi- tions, or from system noise. sector size address range AM42BDS6408H 128 words 000000h?00007fh factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh
october 23, 2003 AM42BDS6408H 23 advance information write protect (wp#) the write protect feature provides a hardware method of protecting the four outermost sectors. this function is provided by the wp# pin and overrides the previ- ously discussed sector protection/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the eight ?out- ermost? 4 kword boot sectors. if the system asserts v ih on the wp# pin, the device reverts to whether sectors 0 ? 3 and 138 ? 141 were last set to be protected or unprotected. that is, sector pro- tection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in ?ppb program command? section on page 38 . note that the wp# pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-indepen- dent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6-9 . to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6-9 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the amd site at the following url: http://www.amd.com/flash/cfi. alternatively, contact an amd representative for copies table 6. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
24 AM42BDS6408H october 23, 2003 advance information table 7. system interface string table 8. device geometry definition addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) addresses data description 27h 0017h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 007dh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
october 23, 2003 AM42BDS6408H 25 advance information table 9. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0011 = 0.13 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 07 = advanced sector protection 4ah 0077h simultaneous operation number of sectors in all banks except boot block 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 01h = dual boot device, 02h = bottom boot device, 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0017h bank a region information. x = number of sectors in bank 59h 0030h bank b region information. x = number of sectors in bank 5ah 0030h bank c region information. x = number of sectors in bank 5bh 0017h bank d region information. x = number of sectors in bank
26 AM42BDS6408H october 23, 2003 advance information table 10. sector address table bank sector sector size address range bank d sa0 4 kwords 000000h-000fffh sa1 4 kwords 001000h-001fffh sa2 4 kwords 002000h-002fffh sa3 4 kwords 003000h-003fffh sa4 4 kwords 004000h-004fffh sa5 4 kwords 005000h-005fffh sa6 4 kwords 006000h-006fffh sa7 4 kwords 007000h-007fffh sa8 32 kwords 008000h-00ffffh sa9 32 kwords 010000h-017fffh sa10 32 kwords 018000h-01ffffh sa11 32 kwords 020000h-027fffh sa12 32 kwords 028000h-02ffffh sa13 32 kwords 030000h-037fffh sa14 32 kwords 038000h-03ffffh sa15 32 kwords 040000h-047fffh sa16 32 kwords 048000h-04ffffh sa17 32 kwords 050000h-057fffh sa18 32 kwords 058000h-05ffffh sa19 32 kwords 060000h-067fffh sa20 32 kwords 068000h-06ffffh sa21 32 kwords 070000h-077fffh sa22 32 kwords 078000h-07ffffh bank c sa23 32 kwords 080000h-087fffh sa24 32 kwords 088000h-08ffffh sa25 32 kwords 090000h-097fffh sa26 32 kwords 098000h-09ffffh sa27 32 kwords 0a0000h-0a7fffh sa28 32 kwords 0a8000h-0affffh sa29 32 kwords 0b0000h-0b7fffh sa30 32 kwords 0b8000h-0bffffh sa31 32 kwords 0c0000h-0c7fffh sa32 32 kwords 0c8000h-0cffffh sa33 32 kwords 0d0000h-0d7fffh sa34 32 kwords 0d8000h-0dffffh sa35 32 kwords 0e0000h-0e7fffh sa36 32 kwords 0e8000h-0effffh sa37 32 kwords 0f0000h-0f7fffh sa38 32 kwords 0f8000h-0fffffh
october 23, 2003 AM42BDS6408H 27 advance information bank c sa39 32 kwords 100000h-107fffh sa40 32 kwords 108000h-10ffffh sa41 32 kwords 110000h-117fffh sa42 32 kwords 118000h-11ffffh sa43 32 kwords 120000h-127fffh sa44 32 kwords 128000h-12ffffh sa45 32 kwords 130000h-137fffh sa46 32 kwords 138000h-13ffffh sa47 32 kwords 140000h-147fffh sa48 32 kwords 148000h-14ffffh sa49 32 kwords 150000h-157fffh sa50 32 kwords 158000h-15ffffh sa51 32 kwords 160000h-167fffh sa52 32 kwords 168000h-16ffffh sa53 32 kwords 170000h-177fffh sa54 32 kwords 178000h-17ffffh sa55 32 kwords 180000h-187fffh sa56 32 kwords 188000h-18ffffh sa57 32 kwords 190000h-197fffh sa58 32 kwords 198000h-19ffffh sa59 32 kwords 1a0000h-1a7fffh sa60 32 kwords 1a8000h-1affffh sa61 32 kwords 1b0000h-1b7fffh sa62 32 kwords 1b8000h-1bffffh sa63 32 kwords 1c0000h-1c7fffh sa64 32 kwords 1c8000h-1cffffh sa65 32 kwords 1d0000h-1d7fffh sa66 32 kwords 1d8000h-1dffffh sa67 32 kwords 1e0000h-1e7fffh sa68 32 kwords 1e8000h-1effffh sa69 32 kwords 1f0000h-1f7fffh sa70 32 kwords 1f8000h-1fffffh bank sector sector size address range
28 AM42BDS6408H october 23, 2003 advance information bank b sa71 32 kwords 200000h-207fffh sa72 32 kwords 208000h-20ffffh sa73 32 kwords 210000h-217fffh sa74 32 kwords 218000h-21ffffh sa75 32 kwords 220000h-227fffh sa76 32 kwords 228000h-22ffffh sa77 32 kwords 230000h-237fffh sa78 32 kwords 238000h-23ffffh sa79 32 kwords 240000h-247fffh sa80 32 kwords 248000h-24ffffh sa81 32 kwords 250000h-257fffh sa82 32 kwords 258000h-25ffffh sa83 32 kwords 260000h-267fffh sa84 32 kwords 268000h-26ffffh sa85 32 kwords 270000h-277fffh sa86 32 kwords 278000h-27ffffh sa87 32 kwords 280000h-287fffh sa88 32 kwords 288000h-28ffffh sa89 32 kwords 290000h-297fffh sa90 32 kwords 298000h-29ffffh sa91 32 kwords 2a0000h-2a7fffh sa92 32 kwords 2a8000h-2affffh sa93 32 kwords 2b0000h-2b7fffh sa94 32 kwords 2b8000h-2bffffh sa95 32 kwords 2c0000h-2c7fffh sa96 32 kwords 2c8000h-2cffffh sa97 32 kwords 2d0000h-2d7fffh sa98 32 kwords 2d8000h-2dffffh sa99 32 kwords 2e0000h-2e7fffh sa100 32 kwords 2e8000h-2effffh sa101 32 kwords 2f0000h-2f7fffh sa102 32 kwords 2f8000h-2fffffh bank sector sector size address range
october 23, 2003 AM42BDS6408H 29 advance information bank b sa103 32 kwords 300000h-307fffh sa104 32 kwords 308000h-30ffffh sa105 32 kwords 310000h-317fffh sa106 32 kwords 318000h-31ffffh sa107 32 kwords 320000h-327fffh sa108 32 kwords 328000h-32ffffh sa109 32 kwords 330000h-337fffh sa110 32 kwords 338000h-33ffffh sa111 32 kwords 340000h-347fffh sa112 32 kwords 348000h-34ffffh sa113 32 kwords 350000h-357fffh sa114 32 kwords 358000h-35ffffh sa115 32 kwords 360000h-367fffh sa116 32 kwords 368000h-36ffffh sa117 32 kwords 370000h-377fffh sa118 32 kwords 378000h-37ffffh bank a sa119 32 kwords 380000h-387fffh sa120 32 kwords 388000h-38ffffh sa121 32 kwords 390000h-397fffh sa122 32 kwords 398000h-39ffffh sa123 32 kwords 3a0000h-3a7fffh sa124 32 kwords 3a8000h-3affffh sa125 32 kwords 3b0000h-3b7fffh sa126 32 kwords 3b8000h-3bffffh sa127 32 kwords 3c0000h-3c7fffh sa128 32 kwords 3c8000h-3cffffh sa129 32 kwords 3d0000h-3d7fffh sa130 32 kwords 3d8000h-3dffffh sa131 32 kwords 3e0000h-3e7fffh sa132 32 kwords 3e8000h-3effffh sa133 32 kwords 3f0000h-3f7fffh sa134 4 kwords 3f8000h-3f8fffh sa135 4 kwords 3f9000h-3f9fffh sa136 4 kwords 3fa000h-3fafffh sa137 4 kwords 3fb000h-3fbfffh sa138 4 kwords 3fc000h-3fcfffh sa139 4 kwords 3fd000h-3fdfffh sa140 4 kwords 3fe000h-3fefffh sa141 4 kwords 3ff000h-3fffffh bank sector sector size address range
30 AM42BDS6408H october 23, 2003 advance information command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 16, ?command definitions,? on page 40 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. see the ?erase suspend/erase resume commands? section on page 36 for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the ?reset command? section on page 33 for more information. see also ?requirements for asynchronous read oper- ation (non-burst)? section on page 12 and ?require- ments for synchronous (burst) read operation? section on page 12 for more information. the asyn- chronous read and synchronous/burst read tables provide the read parameters, and figure 13, ?clk syn- chronous burst mode read (rising active clk),? on page 54 , figure 15, ?synchronous burst mode read,? on page 55 , and figure 28, ?asynchronous mode read with latched addresses,? on page 63 show the timings. set configuration register command se- quence the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. the configuration register must be set before the device will enter burst mode. the configuration register is loaded with a three-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be c0h, address bits a11?a0 should be 555h, and address bits a19?a12 set the code to be latched. the device will power up or after a hardware reset with the default setting, which is in asynchronous mode. the register must be set before the device can enter syn- chronous mode. the configuration register can not be changed during device operations (program, erase, or sector lock). figure 3. synchronous/asynchronous state diagram read mode setting on power-up or hardware reset, the device is set to be in asynchronous read mode. this setting allows the system to enable or disable burst mode during system operations. address a19 determines this setting: ?1? for asynchronous mode, ?0? for synchronous mode. programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. address bits a14?a12 determine the setting (see table 11, ?programmable wait state settings,? on page 31 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (a19 = 0) set burst mode configuration register command for asynchronous mode (a19 = 1)
october 23, 2003 AM42BDS6408H 31 advance information table 11. programmable wait state settings notes: 1. upon power-up or hardware reset, the default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default set- ting. reduced wait-state handshaking option if the device is equipped with the reduced wait-state handshaking option, the host system should set address bits a14?a12 to 010 for the system/device to execute at maximum speed. table 12 describes the typical number of clock cycles (wait states) for various conditions. table 12. wait states for reduced wait-state handshaking notes: 1. if the latched address is 3eh or 3fh (or an address offset from either address by a multiple of 64), add two access cycles to the values listed. 2. in the 8-, 16-, and 32-word burst modes, the address pointer does not cross 64-word boundaries (3fh, or addresses offset from 3fh by a multiple of 64). 3. typical initial access cycles may vary depending on system margin requirements. standard handshaking option for optimal burst mode performance on devices with the standard handshaking option, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. a14 a13 a12 total initial access cycles 000 2 001 3 010 4 011 5 100 6 101 7 (default) 110 reserved 111 reserved v io = 1.8 v system frequency range even initial address odd initial address device speed rating 6 ? 22 mhz 2 2 d (54 mhz) 22 ? 28 mhz 2 3 28 ? 43 mhz 3 4 43 ? 54 mhz 4 5 6 ? 28 mhz 2 2 e (66 mhz) 28 ? 35 mhz 2 3 35 ? 53 mhz 3 4 53 ? 66 mhz 4 5 v io = 1.5 v system frequency range even initial address odd initial address device speed rating 6 ? 18 mhz 2 2 d (54 mhz) 18 ? 22 mhz 2 3 22 ? 33 mhz 3 4 33 ? 45 mhz 4 5 45 ? 54 mhz 5 6 6 ? 23 mhz 2 2 e (66 mhz) 23 ? 28 mhz 2 3 28 ? 42 mhz 3 4 42 ? 56 mhz 4 5 56 ? 66 mhz 5 6
32 AM42BDS6408H october 23, 2003 advance information table 13 describes the typical number of clock cycles (wait states) for various conditions with a14-a12 set to 101. table 13. wait states for standard handshaking * in the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3fh). the autoselect function allows the host system to determine whether the flash device is enabled for handshaking. see the ?autoselect command sequence? section on page 33 for more information. read mode configuration the device supports four different read modes: contin- uous mode, and 8, 16, and 32 word linear wrap around modes. a continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. for example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. the address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. the sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. ta b l e 1 4 shows the address bits and settings for the four read modes. table 14. read mode settings note: upon power-up or hardware reset the default setting is continuous. burst active clock edge configuration by default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. subsequent outputs will also be on the following rising edges, barring any delays. the device can be set so that the falling clock edge is active for all synchro- nous accesses. address bit a17 determines this set- ting; ?1? for rising active, ?0? for falling active. rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. address bit a18 deter- mines this setting; ?1? for rdy active with data, ?0? for rdy active one clock cycle before valid data. in asyn- chronous mode, rdy is an open-drain output. configuration register table 15 shows the address bits that determine the configuration register settings for various device func- tions. conditions at address typical no. of clock cycles after avd# low initial address 7 initial address is 3e or 3fh (or offset from these addresses by a multiple of 64) and is at boundary crossing* 7 burst modes address bits a16 a15 continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1
october 23, 2003 AM42BDS6408H 33 advance information table 15. configuration register note: device will be in the default state upon power-up or hardware reset. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 16, ?command definitions,? on page 40 shows the address and data requirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-sus- pend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the autoselect command. the bank then enters the autoselect mode. no subsequent data will be made available if the autoselect data is read in synchronous mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. read com- mands to other banks will return data from the array. the following table describes the address require- ments for the various autoselect functions, and the resulting data. ba represents the bank address, and address bit function settings (binary) a19 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) a18 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) a17 clock 0 = burst starts and data is output on the falling edge of clk 1 = burst starts and data is output on the rising edge of clk (default) a16 a15 read mode synchronous mode 00 = continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around a14 a13 a12 programmable wait state 000 = data is valid on the 2th active clk edge after avd# transition to v ih 001 = data is valid on the 3th active clk edge after avd# transition to v ih 010 = data is valid on the 4th active clk edge after avd# transition to v ih 011 = data is valid on the 5th active clk edge after avd# transition to v ih 100 = data is valid on the 6th active clk edge after avd# transition to v ih 101 = data is valid on the 7th active clk edge after avd# transition to v ih (default) 110 = reserved 111 = reserved
34 AM42BDS6408H october 23, 2003 advance information sa represents the sector address. the device id is read in three cycles. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend). enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight word electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. the secsi sector is not ac- cessible when the device is executing an embedded program or embedded erase algorithm. ta b l e 1 6 , ?command definitions,? on page 40 shows the address and data requirements for both command sequences. program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 16, ?command defini- tions,? on page 40 shows the address and data require- ments for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by monitoring dq7 or dq6/dq2. refer to the ?write operation status? section on page 43 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to prima- rily program to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. the host system may also ini- tiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles. table 16, ?command definitions,? on page 40 shows the require- ments for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset com- mands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 221eh device id, word 3 (ba) + 0fh 2201h sector protection verification (sa) + 02h 0001 (locked), 0000 (unlocked) indicator bits (ba) + 03h dq15 - dq8 = 0 dq7: factory lock bit 1 = locked, 0 = not locked dq6: customer lock bit 1 = locked, 0 = not locked dq5: handshake bit 1 = reduced wait-state handshake, 0 = standard handshake
october 23, 2003 AM42BDS6408H 35 advance information the device offers accelerated program operations through the acc input. when the system asserts v hh on this input, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to accelerate the operation. figure 4, ?program operation,? on page 35 illustrates the algorithm for the program operation. refer to the erase/program operations table in the ac character- istics section for parameters, and figure 31, ?asyn- chronous program operation timings: avd# latched addresses,? on page 66 and figure 33, ?synchronous program operation timings: we# latched addresses,? on page 68 for timing diagrams. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. ta b l e 1 6 , ?command definitions,? on page 40 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to the ?write operation status? section on page 43 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles cycles in length instead of six cycles. see ta bl e 1 6 , ?command definitions,? on page 40 for details on the unlock bypass command sequences. figure 5, ?erase operation,? on page 37 illustrates the algorithm for the erase operation. refer to the erase/program operations table in the ac character- istics section for parameters and timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 16, ?command defi- nitions,? on page 40 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sec- tors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 16 for program command sequence.
36 AM42BDS6408H october 23, 2003 advance information the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command sequence and any addi- tional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see ?dq3: sector erase timer? section on page 46 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to the ?write operation status? section on page 43 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates t he erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 5, ?erase operation,? on page 37 illustrates the algorithm for the erase operation. refer to the erase/program operations table in the figure , ?ac characteristics,? on page 65 for parameters and timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the figure , ?write operation status,? on page 43 for information on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. refer to the ?write operation status? section on page 43 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the ?AM42BDS6408H boot sector/sector block addresses for protection/unprotection? section on page 16 and ?autoselect command sequence? section on page 33 for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command
october 23, 2003 AM42BDS6408H 37 advance information are ignored. another erase suspend command can be written after the chip has resumed erasing. figure 5. erase operation password program command the password program command permits program- ming the password that is used as part of the hard- ware protection scheme. the actual password is 64-bits long. 4 password program commands are re- quired to program the password. the user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no provisions for entering the 2-cycle unlock cycle, the password program command, and all the password data. there is no special addressing order required for program- ming the password. also, when the password is under- going programming, simultaneous operation is disabled. read operations to any memory location will return the programming status. once programming is complete, the user must issue a read/reset com- mand to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verifi- cation. the password program command is only ca- pable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remain- ing as a ?0?. the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will al- ways drive all f?s onto the dq data bus. also, the device will not operate in simultaneous oper- ation when the password verify command is executed. only the password is returned regardless of the bank address. the lower two address bits (a1?a0) are valid during the password verify. writing the read/reset command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. when the password protection mode locking bit is undergoing programming, simultaneous operation is disabled. once programmed, the pass- word protection mode locking bit cannot be erased! if the password protection mode locking bit is verified as program without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the per- sistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the pass- word mode locking bit from ever being programmed. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program com- mand should be reissued to improve program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. when the persis- tent sector protection mode locking bit is undergoing programming, simultaneous operation is disabled. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 16 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
38 AM42BDS6408H october 23, 2003 advance information secsi sector protection bit program command the secsi sector protection bit program command programs the secsi sector protection bit, which pre- vents the secsi sector memory from being cleared. if the secsi sector protection bit is verified as pro- grammed without margin, the secsi sector protection bit program command should be reissued to improve program margin. exiting the v cc -level secsi sector protection bit program command is accomplished by writing the read/reset command. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully exe- cuted. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the password unlock command is executed. upon set- ting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the read/reset command, only while in the persistent sector protec- tion mode. dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits (a21?a12) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset. exiting the dyb write command is accomplished by writing the read/reset command. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become ac- cessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accomplished by writing password unlock command and data to the de- vice to perform the clearing of the ppb lock bit. the password is 64 bits long, so the user must write the password unlock command 4 times. a1 and a0 are used for matching. writing the password unlock com- mand is not address order specific. the lower address a1?a0= 00, the next password unlock command is to a1?a0= 01, then to a1?a0= 10, and finally to a1?a0= 11. once the password unlock command is entered for all four words, the rdy pin goes low indicating that the device is busy. approximately 1usec is required for each portion of the unlock. once the first portion of the password unlock completes (rdy is not driven and dq6 does not toggle when read), the password un- lock command is issued again, only this time with the next part of the password. four password unlock com- mands are required to successfully clear the ppb lock bit. as with the first password unlock command, the rdy signal goes low and reading the device re- sults in the dq6 pin toggling on successive read oper- ations until complete. it is the responsibility of the microprocessor to keep track of the number of pass- word unlock commands, the order, and when to read the ppb lock bit to confirm successful password un- lock. in order to relock the device into the password mode, the ppb lock bit set command can be re-is- sued. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually pro- grammed (but is bulk erased with the other ppbs). the specific sector address (a21?a12) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been pro- grammed with margin. if the ppb has been pro- grammed without margin, the program command should be reissued to improve the program margin. the ppb program command does not follow the em- bedded program algorithm. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually eras- ing a specific ppb. unlike the ppb program, no spe- cific sector address is required. however, when the ppb erase command is written (60h) and a6 = 1, all sector ppbs are erased in par allel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased with-
october 23, 2003 AM42BDS6408H 39 advance information out margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-era- sure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. dyb write command the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at hardware reset. there is one dyb per sector. if the ppb is set, the sec- tor is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. ppb status command the programming of the ppb for a given sector can be verified by writing a ppb status verify command to the device. ppb lock bit status command the programming of the ppb lock bit for a given sec- tor can be verified by writing a ppb lock bit status ver- ify command to the device. dyb status command the programming of the dyb for a given sector can be verified by writing a dyb status command to the de- vice.
40 AM42BDS6408H october 23, 2003 advance information command definitions table 16. command definitions command sequence (note 1) cycles bus cycles (notes 1?6) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data asynchronous read (note 7) 1 ra rd reset (note 8) 1 xxx f0 autoselect (note 9) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e 221e (ba) x0f 2201 sector lock verify (note 10) 4555 aa2aa55 (sa) 555 90 (sa) x02 (note 10) indicator bits (note 11) 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 (note 11) program 4 555 aa 2aa 55 555 a0 pa data chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 14) 1 ba b0 erase resume (note 15) 1 ba 30 set configuration register (note 16) 3 555 aa 2aa 55 (cr) 555 c0 cfi query (note 17) 1 55 98 unlock bypass mode unlock bypass entry 3 555 aa 2aa 55 555 20 unlock bypass program (notes 12, 13) 2xx a0 pa pd unlock bypass sector erase (notes 12, 13) 2xx 80 sa 30 unlock bypass erase (notes 12, 13) 2 xx 80 xxx 10 unlock bypass cfi (notes 12, 13) 1xx 98 unlock bypass reset 2 xx 90 xxx 00 sector protection command definitions secsi sector secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (notes 18, 19, 21) 6 555 aa 2aa 55 555 60 (sa) ow 68 (sa) ow 48 ow rd (0) password protection password program (notes 18, 23) 4 555 aa 2aa 55 555 38 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3 password verify 4 555 aa 2aa 55 555 c8 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3 password unlock (note 23) 7 555 aa 2aa 55 555 28 xx0 pd0 xx1 pd1 xx2 pd2 xx3 pd3
october 23, 2003 AM42BDS6408H 41 advance information legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the rising edge of the avd# pulse or active edge of clk which ever comes first. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. ba = address of the bank (a21, a20, a19) that is being switched to autoselect mode, is in bypass mode, or is being erased. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register address bits a19?a12. ow = address (a7?a0) is (00011010). pd3?pd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. pl = address (a7-a0) is (00001010) rd(0) = dq0 protection indicator bit. if protected, dq0 = 1, if unprotected, dq0 = 0. rd(1) = dq1 protection indicator bit. if protected, dq1 = 1, if unprotected, dq1 = 0. sl = address (a7-a0) is (00010010) wd= write data. see ?configuration register? definition for specific write data wp = address (a7-a0) is (00000010) notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pd3-pd0. 5. unless otherwise noted, address bits a21?a12 are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see the autoselect command sequence section for more information. 10. the data is 0000h for an unlocked sector and 0001h for a locked sector 11. dq15 - dq8 = 0, dq7: factory lock bit (1 = locked, 0 = not locked), dq6: customer lock bit (1 = locked, 0 = not locked), dq5: handshake bit (1 = reduced wait-state handshake, 0 = standard handshake), dq4 - dq0 = 0 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. ppb command s ppb program (notes 18, 19, 21) 6 555 aa 2aa 55 555 60 (sa) + wp 68 (sa) + wp 48 xx rd (0) all ppb erase (notes 18, 19, 22, 24) 6 555 aa 2aa 55 555 60 wp 60 wp 40 xx rd (0) ppb status (note 25) 4 555 aa 2aa 55 (ba) 555 90 (sa) x02 rd (0) ppb lock bit ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status (note 19) 4 555 aa 2aa 55 (ba) 555 58 sa rd (1) dyb dyb write 4 555 aa 2aa 55 555 48 sa x1 dyb erase 4 555 aa 2aa 55 555 48 sa x0 dyb status 4 555 aa 2aa 55 (ba) 555 58 sa rd (0) password protection mode locking bit program (notes 18, 19, 21) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd (0) persistent protection mode locking bit program (notes 18, 19, 21) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd (0) password protection mode locking bit read (notes 18, 19, 21) 4 555 aa 2aa 55 555 60 pl rd (0) persistent protection mode locking bit read (notes 18, 19, 21) 4 555 aa 2aa 55 555 60 sl rd (0) command sequence (note 1) cycles bus cycles (notes 1?6) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
42 AM42BDS6408H october 23, 2003 advance information 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. see ?set configuration register command sequence? for details. 17. command is valid when device is ready to read array data or when device is in autoselect mode. 18. the reset command returns the device to reading the array. 19. regardless of clk and avd# interaction or control register bit 15 setting, command mode verifies are always asynchronous read operations. 20. acc must be at v hh during the entire operation of this command 21. the fourth cycle progra ms the addressed locking bit. the fifth and sixth cycles are used to validate whether the bit has been fully programmed. if dq0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 22. the fourth cycle erases all ppbs. the fifth and sixth cycles are used to validate whether the bits have been fully erased. if dq0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 23. the entire four bus-cycle sequence must be entered for each portion of the password. 24. before issuing the erase command, all ppbs should be programmed in order to prevent over-erasure of ppbs. 25. in the fourth cycle, 01h indicates ppb set; 00h indicates ppb not set.
october 23, 2003 AM42BDS6408H 43 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 18, ?write operation status,? on page 47 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algo- rithm is in progress or comp leted, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-dq0 will appear on succes- sive read cycles. table 18, ?write operation status,? on page 47 shows the outputs for data# polling on dq7. figure 6, ?data# polling algorithm,? on page 43 shows the data# polling algorithm. figure 37, ?data# polling timings (during embedded algorithm),? on page 72 in the ac characteristics section shows the data# polling timing diagram. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
44 AM42BDS6408H october 23, 2003 advance information rdy: ready the rdy is a dedicated output that, when the device is configured in the synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. the rdy pin is only controlled by ce#. using the rdy configuration command sequence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. the following conditions cause the rdy output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3fh. when the device is configured in asynchronous mode, the rdy is an open-drain output pin which indicates whether an embedded algorithm is in progress or com- pleted. the rdy status is valid after the rising edge of the final we# pulse in the command sequence. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is in high imped- ance (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 18, ?write operation status,? on page 47 shows the outputs for rdy. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 7, ?toggle bit algorithm,? on page 45 , ?dq6: toggle bit i? on page 44 , figure 38, ?toggl e bit timings (during embedded algorithm),? on page 72 (toggle bit timing diagram), and table 17, ?dq6 and dq2 indica- tions,? on page 46 . toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state.
october 23, 2003 AM42BDS6408H 45 advance information figure 7. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by com- parison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode informa- tion. refer to table 17, ?dq6 and dq2 indications,? on page 46 to compare outputs for dq2 and dq6. see the following for additional information: figure 7, ?toggle bit algorithm,? on page 45, ?dq6: toggle bit i? on page 44, figure 38, ?toggle bit timings (during embedded algorithm),? on page 72 , and table 17, ?dq6 and dq2 indications,? on page 46 . start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq7-dq0) address = va dq6 = toggle? read byte twice (dq7-dq0) adrdess = va read byte (dq7-dq0) address = va fail pass note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
46 AM42BDS6408H october 23, 2003 advance information table 17. dq6 and dq2 indications reading toggle bits dq6/dq2 refer to figure 7, ?toggle bit algorithm,? on page 45 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the firs t. if the toggle bit is not tog- gling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation ( figure 7, ?toggle bit algorithm,? on page 45 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully com- pleted. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also ?sector erase command sequence? on page 35 . after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
october 23, 2003 AM42BDS6408H 47 advance information device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 18 shows the status of dq3 relative to the other status bits. table 18. write op eration status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. 4. the system may read either asynchronously or synchronously (burst) while in erase suspend. 5. the rdy pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. this is available in the asynchronous mode only. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) rdy (note 5) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read (note 4) erase suspended sector 1 no toggle 0 n/a toggle high impedance non-erase suspended sector data data data data data high impedance erase-suspend-program dq7# toggle 0 n/a n/a 0
48 AM42BDS6408H october 23, 2003 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied. . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) . . . . . . . ?0.5 v to v io + 0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v a9, reset#, acc (note 1) . . . . . ?0.5 v to +12.5 v output short circuit current (note 3) . . . . . . 100 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8. maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 9. 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 3. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indicated in the operational sections of th is data sheet is not implied. exposure of the device to absolute maximum rating condi- tions for extended periods may affect device reliability. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . .+1.65 v to +1.95 v . . . . . . . . . . . . . . . . . . . . . . . . . . v cc >= v io - 100mv v io supply voltages: . . . . . . . . . . +1.65 v to +1.95 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
october 23, 2003 AM42BDS6408H 49 advance information dc characteristics cmos compatible note: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v io = v cc 3. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . 6. total current during accelerated programming is the sum of v acc and v cc currents. parameter description test conditions note: 1 & 2 min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 9 17 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 8 15.5 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 7 14 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 8 50 200 a i io1 v io non-active output oe# = v ih 0.2 10 a i cc1 v cc active asynchronous read current (note 3) ce# = v il , oe# = v ih , we# = v ih 10 mhz tbd tbd ma 5 mhz 12 16 ma 1 mhz 3.5 5 ma i cc2 v cc active write current (note 4) ce# = v il , oe# = v ih , acc = v ih 15 40 ma i cc3 v cc standby current (note 5) ce# = reset# = v cc 0.2 v 1 40 a i cc4 v cc reset current reset# = v il, clk = v il 140a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih 25 60 ma i cc6 v cc sleep current ce# = v il , oe# = v ih 140a i acc accelerated program current (note 6) ce# = v il , oe# = v ih, v acc = 12.0 0.5 v v acc 715ma v cc 510ma v il input low voltage v io = 1.8 v ?0.4 0.4 v v io = 1.5 v tbd tbd v ih input high voltage v io = 1.8 v v io ? 0.4 v io + 0.4 v io = 1.5 v tbd tbd v v ol output low voltage i ol = 100 a, v io = v cc = v cc min 0.1 v v oh output high voltage i oh = ?100 a, v io = v cc = v cc min v io ? 0.1 v v id voltage for autoselect and temporary sector unprotect v cc = 1.8 11.5 12.5 v v hh voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
50 AM42BDS6408H october 23, 2003 advance information notes: 1. typical values measured at v cc = 2.0 v, t a = 25 c. not 100% tested. 2. undershoot is ?1.0 v when pulse width 20 ns. 3. overshoot is v cc + 1.0 v when pulse width 20 ns. 4. overshoot and undershoot are sampled, not 100% tested. sram dc and operating characteristics parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ?1.0 1.0 a i lo output leakage current ce1#s = v ih , ce2s = v il or oe# = v ih or we# = v il , v io = v ss to v cc ?1.0 1.0 a i cc operating power supply current i io = 0 ma, ce1#s = v il , ce2s = we# = v ih , v in = v ih or v il 5ma i cc1 s average operating current cycle time = 1 s, 100% duty, i io = 0 ma, ce1#s 0.2 v, ce2 v cc ? 0.2 v, v in 0.2 v or v in v cc ? 0.2 v 15ma i cc2 s average operating current cycle time = min., i io = 0 ma, 100% duty, ce1#s = v il , ce2s = v ih , v in = v il = or v ih 815ma v ol output low voltage i ol = 0.1 ma 0.2 v v oh output high voltage i oh = ?0.1 ma 1.4 v i sb1 standby current (cmos) ce1#s v cc ? 0.2 v, ce2 v cc ? 0.2 v (ce1#s controlled) or ce2 0.2 v (ce2s controlled), cios = v ss or v cc , other input = 0 ~ v cc 225a v il input low voltage ?0.2 (note 2) 0.4 v v ih input high voltage 1.4 v cc +0. 2 (note 3) v
october 23, 2003 AM42BDS6408H 51 advance information test conditions table 19. test specifications key to switching waveforms switching waveforms c l device under te s t figure 10. test setup test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 11. input waveforms and measurement levels v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
52 AM42BDS6408H october 23, 2003 advance information ac characteristics v cc power-up figure 12. v cc power-up diagram parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time min 50 s t rsth reset# low hold time min 50 s v cc v io reset# t vcs t rsth t vios
october 23, 2003 AM42BDS6408H 53 advance information synchronous/burst read ( v io = 1.8 v ) notes: 1. addresses are latched on the first of either the active edge of clk or the rising edge of avd#. 2. please contact amd for availability of v io = 1.5 v devices. parameter description e6, e7, e8, e9 (66 mhz) d6, d7, d8, d9 (54 mhz) unit jedec standard t iacc latency (even address in reduced wait-state handshake mode) max 56 69 ns t iacc latency (standard handshake or odd address in reduced wait-state handshake mode max 71 87.5 ns t bacc burst access time valid clock to output delay max 11 13.5 ns t acs address setup time to clk (note 1) min 4 5 ns t ach address hold time from clk (note 1) min 6 7 ns t bdh data hold time from next clock cycle min 3 4 ns t cr chip enable to rdy valid max 11 13.5 ns t oe output enable to output valid max 11 13.5 ns t cez chip enable to high z max 8 10 ns t oez output enable to high z max 8 10 ns t ces ce# setup time to clk min 4 5 ns t rdys rdy setup time to clk min 4 5 ns t racc ready access time from clk max 11 13.5 ns t aas address setup time to avd# (note 1) min 4 5 ns t aah address hold time to avd# (note 1) min 6 7 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 4 5 ns t avd avd# pulse min 10 12 ns t acc access time max 50 55 ns t cka clk to access resume max 11 13.5 ns t ckz clk to high z max 8 10 ns t oes output enable setup time min 4 5 ns t rcc read cycle for continuous suspend max 1 ms
54 AM42BDS6408H october 23, 2003 advance information ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 13. clk synchronous burst mode read (rising active clk) notes: 1. figure shows total number of wait states set to four cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active falling edge. 2. if any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 14. clk synchronous burst mode read (falling active clock) da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t acc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1 2 34 56 7 t rdys t bacc t cr da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t oez t cez t iacc t acc t bdh 4 cycles for initial access shown. t racc hi-z hi-z hi-z 12345 t rdys t bacc t cr
october 23, 2003 AM42BDS6408H 55 advance information ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 15. synchronous burst mode read note: figure assumes 7 wait states for initial access and automatic detect synchronous read. d0?d7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 7th address in range (a6). see ?requirements for synchronous (burst) read operation?. the set configuration register command sequence has been written with a18=1; device will output rdy with valid data. figure 16. 8-word linear burst with wrap around da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc t cr d6 d7 oe# data addresses a6 avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh d0 d1 d5 d6 7 cycles for initial access shown. hi-z t racc 1 234567 t rdys t bacc t acc t cr
56 AM42BDS6408H october 23, 2003 advance information ac characteristics note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy one cycle before valid data. figure 17. linear burst with rdy set one cycle before data d1 d0 d2 d3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1 23456 t rdys t bacc t acc t cr
october 23, 2003 AM42BDS6408H 57 advance information ac characteristics note: figure is for any even address other than 3eh (or multiple thereof). figure 18. reduced wait-state handshake burst suspend/resume at an even address note: figure is for any odd address other than 3fh (or multiple thereof). figure 19. reduced wait-state handshake bu rst suspend/resume at an odd address d(23) d(24) d(23) d(20) d(21) d(22) d(23) addresses avd# data rdy d(20) t oes t oes t cka t ckz x+1 x+2 x+3 x+4 x+5 x+6 x x+7 x+8 oe# t racc suspend resume clk t racc d(25) d(27) d(26) d(23) d(24) d(25) d(25) addresses avd# data rdy d(23) t oes t oes t cka t ckz x+1 x+2 x+3 x+4 x+5 x+6 x x+7 x+8 oe# t racc suspend resume clk t racc
58 AM42BDS6408H october 23, 2003 advance information ac characteristics figure 20. reduced wait-state handshake burst suspe nd/resume at address 3eh (or offset from 3eh) figure 21. reduced wait-state handshake burst suspend/resume at address 3fh (or offset from 3fh by a multiple of 64) addresses avd# data rdy d(3e) t oes t oes t cka t ckz oe# d(40) d(3f) d(3f) d(3f) suspend resume d(41) d(41) d(41) clk x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 x+9 x+10 t racc d(3e) d(42) d(41) t racc addresses avd# data rdy d(3f) t oes t oes t cka t ckz oe# d(41) d(3f) d(3f) d(40) suspend resume d(41) d(41) d(41) t racc clk x x+1 x+2 x+3 x+4 x+5 x+6 x+7 x+8 x+9 x+10 d(3f) d(43) d(42) t racc t racc
october 23, 2003 AM42BDS6408H 59 advance information ac characteristics note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. 1) rdy goes low during the two-cycle latency during a boundary crossing. 2) rdy stays high when a burst sequence crosses no boundaries. figure 22. standard handshake burst suspend prior to initial access note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. 1) burst suspend during the initial synchronous access 2) burst suspend after one clock cycle following the initial synchronous access figure 23. standard handshake burst suspend at or after inital access addresses a(n) avd# data(2) rdy(2) rdy(1) t oes t oes t cka t racc t racc 1 234 5 6 7 x+1 x+2 x+3 x+4 x+5 x+6 x x+7 x+8 oe# data(1) t acc d(40) d(3f) d(n) d(n+1) d(n+2) 3f 3f clk d(n) d(n+1) d(n+2) d(n+3) d(n+4) d(n+5) d(n+6) suspend resume addresses a(n) avd# oe#(1) data(1) data(2) oe#(2) rdy(1) d(n) d(n+1) suspend resume t acc t racc t oes t cka d(n) t oes 1 234 5 6 7 8 9 x x+1 x+2 x+3 clk t racc t oes t racc t cka d(n+1) d(n+2) d(n) d(n+1) t racc t racc t racc t ckz rdy(2)
60 AM42BDS6408H october 23, 2003 advance information ac characteristics note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. figure 24. standard handshake burst suspend at address 3fh (starting address 3dh or earlier) note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. 1) address is 3eh or offset by a multiple of 64 (40h) 2) address is 3fh or offset by a multiple of 64 (40h) figure 25. standard handshake burst suspend at address 3eh/3fh (without a valid initial access) addresses a(3d) avd# oe# data rdy d(3f) d(3f) d(3f) d(4d) suspend resume t acc t racc t oes t oes t cka t cka d(3d) t racc 1 234 5 6 7 8 9 x x+1 x+2 x+3 x+4 x+5 clk t racc d(3e) d(3f) t oes t ckz addresses(1) a(3e) avd# clk 1 23 4 5 67 x+1 x+2 x+3 x+4 x+5 x+6 x oe# data(1) addresses(2) data(2) rdy(2) rdy(1) d(3e) d(3f) d(41) d(40) d(42) suspend resume t oes t acc t racc t ckz t oes t oes t cka a(3f) 8 d(3f) t racc t racc t racc t racc t racc d(40) d(42) d(41) d(43) d(3e) d(3f)
october 23, 2003 AM42BDS6408H 61 advance information ac characteristics note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. 1) address 3eh or offset by a multiple of 64 (40h) 2) address is 3fh or offset by a multiple of 64 (40h) figure 26. standard handshake burst susp end at address 3eh/3fh (with 1 access clk) note: figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence has been written with a18=0; device will output rdy with valid data. 1) device crosses a page boundary prior to t rcc 2) device neither crosses a page boundary nor latches a new address prior to t rcc figure 27. read cycle for continuous suspend addresses(1) a(3e) avd# clk 1 23 4 5 67 x+1 x+2 x+3 x+4 x+5 x+6 x oe# data(1) addresses(2) data(2) rdy(2) (odd) rdy(1) (even) d(3e) d(3f) d(41) d(40) d(42) d(40) d(42) d(41) d(43) suspend resume t oes t acc t racc t ckz t oes t oes t cka a(3f) 8 d(3f) d(3f) 9 t racc d(40) t racc t racc t racc t racc addresses a(n) avd# data(2) ce# rdy d(n) ??? t oes t oes t cka t racc t rcc t rcc ??? 1 234 5 6 7 x+1 x+2 x+3 x+4 x+5 x+6 x x+7 x+8 oe# data(1) t acc d(40) d(3f) d(n) d(n+1) d(n+2) d(3f) d(3f) clk suspend resume
62 AM42BDS6408H october 23, 2003 advance information ac characteristics asynchronous mode read ( v io = 1.8 v) notes: 1. asynchronous access time is from the last of either stable addresses or the falling edge of avd#. 2. not 100% tested. parameter description e3, e4, e8, e9 (66 mhz) d6, d7, d8, d9 (54 mhz) unit jedec standard t ce access time from ce# low max 50 tbd ns t acc asynchronous access time (note 1) max 50 tbd ns t avdp avd# low time min 10 12 ns t aavds address setup time to rising edge of avd min 4 5 ns t aavdh address hold time from rising edge of avd min 6 7 ns t oe output enable to output valid max 11 13.5 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 8 10 ns t oez output enable to high z (note 2) max 8 10 ns t cas ce# setup time to avd# min 0 ns
october 23, 2003 AM42BDS6408H 63 advance information ac characteristics note: ra = read address, rd = read data. figure 28. asynchronous mode read with latched addresses note: ra = read address, rd = read data. figure 29. asynchronous mode read t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez t aavdh t avdp t aavds avd# ra t cas t ce we# addresses ce# oe# valid rd t acc t oeh t oe data t oez avd# ra
64 AM42BDS6408H october 23, 2003 advance information ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp figure 30. reset timings
october 23, 2003 AM42BDS6408H 65 advance information ac characteristics erase/program operations (v io = 1.8 v) notes: 1. not 100% tested. 2. asynchronous mode allows the asynchronous program operation only. synchronous mode allows both asynchronous and synchronous p rogram operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we# or rising edge of avd#. in synchro nous program operation timing, addresses are latched on the first of either the falling edge of we# or the active edge of clk. 4. see the ?erase and programming performance? section for more information. 5. does not include the preprogramming time. parameter description e6, e7, e8, e9 (66 mhz) d6, d7, d8, d9 (54 mhz) unit jedec standard t avav t wc write cycle time (note 1) min 50 55 ns t avwl t as address setup time (notes 2, 3) synchronous min 45 ns asynchronous 0 t wlax t ah address hold time (notes 2, 3) synchronous min 67 ns asynchronous 20 20 t avdp avd# low time min 10 12 ns t dvwh t ds data setup time min 20 45 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 20 30 ns t whwl t wph write pulse width high min 20 20 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 4) typ 9 s t whwh1 t whwh1 accelerated programming operation (note 4) typ 4 s t whwh2 t whwh2 sector erase operation (notes 4, 5) ty p 0.4 sec chip erase operation (notes 4, 5) 54 t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 0 ns t avsw avd# setup time to we# min 4 5 ns t avhw avd# hold time to we# min 4 5 ns t acs address setup time to clk (notes 2, 3) min 4 5 ns t ach address hold time to clk (notes 2, 3) min 6 7 ns t avhc avd# hold time to clk min 4 5 ns t csw clock setup time to we# min 5 ns
66 AM42BDS6408H october 23, 2003 advance information ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the configuration register. figure 31. asynchronous program operat ion timings: avd# latched addresses oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph pa t vcs t cs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h 555h pd
october 23, 2003 AM42BDS6408H 67 advance information ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is independent of the set device read mode bit in the configuration register. figure 32. asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t as t avsw t avhw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs
68 AM42BDS6408H october 23, 2003 advance information ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 33. synchronous program operation timings: we# latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t ach t avch t csw
october 23, 2003 AM42BDS6408H 69 advance information ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a21?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 34. synchronous program operat ion timings: clk latched addresses oe# ce# data addresses avd# we# clk v cc 555h pd t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t cas t ah t avch t csw
70 AM42BDS6408H october 23, 2003 advance information ac characteristics figure 35. chip/sector erase command sequence notes: 1. sa is the sector address for sector erase. 2. address bits a21?a12 are don?t cares during unlock cycles in the command sequence. oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
october 23, 2003 AM42BDS6408H 71 advance information ac characteristics note: use setup and hold times from conventional program operation. figure 36. accelerated unlock bypass programming timing ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 s v il or v ih t vid t vids
72 AM42BDS6408H october 23, 2003 advance information ac characteristics notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. 3. while in asynchronous mode, rdy will be low while the device is in embedded erase or programming mode. figure 37. data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. while in asynchronous mode, rdy will be low while the device is in embedded erase or programming mode. figure 38. toggle bit timings (during embedded algorithm) we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data
october 23, 2003 AM42BDS6408H 73 advance information ac characteristics notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (a18 = 0 in the configuration register). when a18 = 1 in the configuration register, rdy is active on e clock cycle before data. figure 39. synchronous data polling timings/toggle bit timings ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 40. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
74 AM42BDS6408H october 23, 2003 advance information ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from rdy high for temporary sector unprotect min 4 s reset# t vidr v id v il or v ih v id v il or v ih ce# we# rdy t vidr t rsp program or erase command sequence t rrb figure 41. temporary sector unprotect timing diagram
october 23, 2003 AM42BDS6408H 75 advance information ac characteristics sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 42. sector/sector block protect and unprotect timing diagram
76 AM42BDS6408H october 23, 2003 advance information ac characteristics) notes: 1. rdy active with data (a18 = 0 in the configuration register). 2. rdy active one clock cycle before data (a 18 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device not crossing a bank in the process of performing an erase or program. 4. if the starting address latched in is either 3eh or 3fh (or some 64 multiple of either), there is no additional 2 cycle laten cy at the boundary crossing. figure 43. latency with boundary crossing clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy(1) data address boundary occurs every 64 words, beginning at address 00003fh: 00007fh, 0000bfh, etc.) address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 41 42 43 latency rdy(2) latency t racc t racc t racc t racc
october 23, 2003 AM42BDS6408H 77 advance information ac characteristics notes: 1. rdy active with data (a18 = 0 in the configuration register). 2. rdy active one clock cycle before data (a 18 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device crossing a bank in the process of performing an erase or program. figure 44. latency with boundary crossing into program/erase bank clk address (hex) c60 c61 c62 c63 c63 c63 c64 d60 d61 d62 d63 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh: (00007fh, 0000bfh, etc.) address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 latency rdy(2) latency t racc t racc t racc t racc invalid
78 AM42BDS6408H october 23, 2003 advance information ac characteristics wait state decoding addresses: a14, a13, a12 = ?111? ? reserved a14, a13, a12 = ?110? ? reserved a14, a13, a12 = ?101? ? 5 programmed, 7 total a14, a13, a12 = ?100? ? 4 programmed, 6 total a14, a13, a12 = ?011? ? 3 programmed, 5 total a14, a13, a12 = ?010? ? 2 programmed, 4 total a14, a13, a12 = ?001? ? 1 programmed, 3 total a14, a13, a12 = ?000? ? 0 programmed, 2 total note: figure assumes address d0 is not at an address boundary, active clock edge is rising, and wait state is set to ?101?. figure 45. example of wait states insertion data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following avd# falling edge rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles p ro g rammed 45
october 23, 2003 AM42BDS6408H 79 advance information ac characteristics note: breakpoints in waveforms indicate that system may alternately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid informatio n. figure 46. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
80 AM42BDS6408H october 23, 2003 advance information sram ac characteristics read cycle note: ce1#s = oe# = v il , ce2s = we# = v ih , ub#s and/or lb#s = v il figure 47. sram read cycle?address controlled parameter symbol description e6, e7, d6, d7 e8, e9, d8, d9 unit t rc read cycle time min 55 70 ns t aa address access time max 55 70 ns t co1 , t co2 chip enable to output max 55 70 ns t oe output enable access time max 25 35 ns t ba lb#s, ub#s to access time max 55 70 ns t lz1 , t lz2 chip enable (ce1#s low and ce2s high) to low-z output min 10 ns t blz ub#, lb# enable to low-z output min 10 ns t olz output enable to low-z output min 5 ns t hz1 , t hz2 chip disable to high-z output max 25 ns t bhz ub#s, lb#s disable to high-z output max 25 ns t ohz output disable to high-z output max 25 ns t oh output data hold from address change min 10 ns address data out previous data valid data valid t aa t rc t oh
october 23, 2003 AM42BDS6408H 81 advance information sram ac characteristics figure 48. sram read cycle notes: 1. we# = v ih . 2. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. data valid high-z t rc ce#1s address oe# data out t oh t aa t co1 t oe t olz t blz t lz t ohz t hz ce2s t co2
82 AM42BDS6408H october 23, 2003 advance information sram ac characteristics write cycle notes: 1. we# controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 49. sram write cycle?we# control parameter symbol description e6, e7, d6, d7 e8, e9, d8, d9 unit t wc write cycle time min 55 70 ns t cw chip enable to end of write min 45 60 ns t as address setup time min 0 ns t aw address valid to end of write min 45 60 ns t bw ub#s, lb#s to end of write min 45 60 ns t wp write pulse time min 45 50 ns t wr write recovery time min 0 ns t whz write to output high-z min 0 ns max 20 t dw data to write time overlap min 30 ns t dh data hold from write time min 0 ns t ow end write to output low-z min 5 ns address ce1#s data undefined we# data in data out t wc t cw (see note 1) t aw high-z high-z data valid ce2s t cw (see note 1) t wp (see note 4) t as (see note 3) t wr t dw t dh t ow t whz
october 23, 2003 AM42BDS6408H 83 advance information sram ac characteristics notes: 1. ce1#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 50. sram write cycle?ce1#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t as (see note 2 ) t bw t cw (see note 3) t wr (see note 4) t wp (see note 5) t dw t dh
84 AM42BDS6408H october 23, 2003 advance information sram ac characteristics notes: 1. ub#s and lb#s controlled. 2. t cw is measured from ce1#s going low to the end of write. 3. t wr is measured from the end of write to the address change. t wr applied in case a write ends as ce1#s or we# going high. 4. t as is measured from the address valid to the beginning of write. 5. a write occurs during the overlap (t wp ) of low ce#1 and low we#. a write begins when ce1#s goes low and we# goes low when asserting ub#s or lb#s for a single byte operation or simult aneously asserting ub#s and lb#s for a double byte operation. a write ends at the earliest transition when ce1#s goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. figure 51. sram write cycle?ub#s and lb#s control address data valid ub#s, lb#s we# data in data out high-z high-z t wc ce1#s ce2s t aw t bw t dw t dh t wr (see note 3) t as (see note 4) t cw (see note 2) t cw (see note 2) t wp (see note 5)
october 23, 2003 AM42BDS6408H 85 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 1 million cycles. additionally, programming typicals assumes a checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.65 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 16, ?command definitions,? on page 40 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1 million cycles. bga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 32 kword 0.4 5 s excludes 00h programming prior to erasure (note 4) 4 kword 0.2 5 chip erase time 54 s word programming time 9 210 s excludes system level overhead (note 5) accelerated word programming time 4 120 s chip programming time (note 3) 38 114 s excludes system level overhead (note 5) accelerated chip programming time 17 50 s parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
86 AM42BDS6408H october 23, 2003 advance information physical dimensions tlb 089?89-ball fine-pitch ball grid array (fbga) 10 x 8 mm package note: bsc is an ansi standard for basic space centering 3294\ 16-038.22 a package tlb089 jedec n/a 10.00 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 10.00 bsc. body size e 8.00 bsc. body size d1 7.20 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 10 matrix size d direction me 10 matrix size e direction n 89 ball count b 0.33 --- 0.43 ball diameter ee 0.80 bsc ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc solder ball placement b10,c1,c10,d1,d10,g1,g10 depopulated solder balls h1,h10,j1,j10 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 index mark 89x c 0.15 (2x) (2x) c 0.15 b a 6 b 0.20 c c 0.15 0.08 m m c c ab d e pin a1 c top view side view corner a2 a1 a 0.08 ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7
october 23, 2003 AM42BDS6408H 87 advance information revision summary revision a (july 14, 2003) initial release. revision a+1 (july 15, 2003) corrected ordering information opns. revision a+2 (july 21, 2003) corrected typos in datasheet regarding package name. revision a+3 (october 23, 2003) corrected globally all psram to sram. remove 80 mhz option throughout. trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .
?2003 advanced micro devices, inc . 01/03 printed in usa one amd place, p.o. box 3453, sunnyvale, ca 94088-3453 408-732-2400 twx 910-339-9280 telex 34-6306 800-538-8450 http://www.amd.com advanced micro devices reserves the right to make changes in its product without notice in order to impr ove design or performance characteristics.the performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. for specific testing details, contact your local amd sales representativ e.the company assumes no responsibility for the use of any circuits described herein. ? advanced micro devices, inc. all rights reser ved. amd, the amd arrow logo and combination thereof, are trademarks of advanced micro devices, inc. other product names are for informational purposes only and may be trademarks of their respective companies. north america alabama . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (256)830-9192 arizona . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)242-4400 california, irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)450-7500 sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)732-2400 colorado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)741-2900 connecticut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (203)264-7800 florida, clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 2 7)793-0055 miami (lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (305)820-1113 georgia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)814-0224 illinois, chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (630)773-4422 massachusetts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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(703)736-9568 international australia, north ryde . . . . . . . . . . . . . . . . . . . . . . . tel(61)2-88-777-222 belgium, antwerpen . . . . . . . . . . . . . . . . . . . . . . . .tel(32)3-248-43-00 brazil, san paulo . . . . . . . . . . . . . . . . . . . . . . . . . . tel(55)11-5501-2105 china, beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)10-6510-2188 shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)21-635-00838 shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(86)755-246-1550 finland, helsinki . . . . . . . . . . . . . . . . . . . . . . tel(358)881-3117 france, paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(33)-1-49751010 germany, bad homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(49)-6172- 92670 munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(49)-89-450530 hong kong, causeway bay . . . . . . . . . . . . . . . . . . . tel(85)2-2956-0388 italy, milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(39)-02-381961 india, new delhi . . . . . . . . . . . . . . . . . . . . . . . . . . tel(91)11-623-8620 japan, osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(81)6-6243-3250 tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tel(81)3-3346-7600 korea, seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(82)2-3468-2600 russia, moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(7)-095-795-06-22 sweden, stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(46)8-562-540-00 taiwan,taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(886)2-8773-1555 united kingdom, frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(44)1276-803100 haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tel(44)1942-272888 representatives in u.s. and canada arizona, tempe - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (480)839-2320 california, calabasas - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (818)878-5800 irvine - centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)261-2123 san diego - centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (858)278-4950 santa clara - fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)350-4800 canada, burnaby, b.c. - davetek marketing. . . . . . . . . . . . . . . . . . . . (604)430-3680 calgary, alberta - davetek marketing. . . . . . . . . . . . . . . . . (403)283-3577 kanata, ontario - j-squared tech. . . . . . . . . . . . . . . . . . . . (613)592-9540 mississauga, ontario - j-squared tech. . . . . . . . . . . . . . . . . . (905)672-2030 st laurent, quebec - j-squared tech. . . . . . . . . . . . . . . . (514)747-1211 colorado, golden - compass marketing . . . . . . . . . . . . . . . . . . . . . . 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(781)238-0870 michigan, brighton - sai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (810)227-0007 minnesota, st. paul - cahill, schmitz & cahill, inc. . . . . . . . . . . . . . . . . . (651)699-0200 missouri, st. louis - lorenz sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558 new jersey, mt. laurel - sj associates . . . . . . . . . . . . . . . . . . . . . . . . . (856)866-1234 new york, buffalo - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . . . .(716)741-7116 east syracuse - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343 pittsford - nycom, inc. . . . . . . . . . . . . . . . . . . . . . . . . . . (716)586-3660 rockville centre - sj associates . . . . . . . . . . . . . . . . . . . . (516)536-4242 north carolina, raleigh - quantum marketing . . . . . . . . . . . . . . . . . . . . . . (919)846-5728 ohio, middleburg hts - dolfuss root & co. . . . . . . . . . . . . . . . . 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(+562)264-0993 columbia, bogota - dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(571)410-4182 mexico, guadalajara - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . ( 5 23)817-3900 mexico city - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . ( 5 25)752-2727 monterrey - latinrep/ww rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828 puert o rico, boqueron - infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)851-6000 sales offices and representatives es

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